HP INVENTS—AGAIN Nanowires For Interconnects
As you’re probably aware, fending off Moore’s Law-whether by paradigm shift or novel nanotechnological technique-is what exciting news in chip design has been all about in recent years. Reversible computing and DNA computing and other “computings” are being heavily researched, as are solutions such as using nanotubes in transistors.
HP has once again validated its claim to its own tagline, “Invent,” with research that proves it is possible to do away with copper interconnects in chips, by using grids of nanowires. See figure below: it shows the structure of HP’s proposed “crossbar” network of nanowires. Two layers of crossbars with orientations perpendicular to each other form a sandwich outside a layer of silicon transistors. The transistors and other functional blocks in the chip communicate through “dynamic” (meaning non-hardwired) connections created in the crossbars.
Think of a nanowire as just a wire on the nanoscale-specifically, with a width in the range of tens of nanometres. Because of their extreme thinness, they are often referred to as one-dimensional structures.
The new design will achieve three objectives: reducing size, increasing performance, and reducing power consumption.
It should be obvious that chips will shrink drastically once the interconnects are gotten rid of. The beauty of the crossbar method is that traditional transistors can still be used.
The company has thus far created a simulation of a field-programmable gate array (FPGA) with a crossbar grid, and hopes to have a prototype by the end of the year. (An FPGA is a type of programmable chip; the simulation essentially maps the intended circuit to the nanowire structure.) The timeframe for commercial chips using the crossbar grid structure is 2010-HP says it is possible for the concept to be incorporated into chips of other types, though the simulation only demonstrated it for FPGAs.
With the FPGA as an example, the functional blocks are hardwired to each other through interconnects, so an increase in the number of functional blocks leads to a “geometric” increase in the number of data pathways. Now, the pathways themselves could consume 80 per cent of available chip area. The crossbar system would result in an “intelligent communications system” that would only connect functional blocks when they need to be connected.
In other chips, with a dynamic network performing the role of interconnects, some transistor areas could be turned off when not in use, thus saving on power.
According to HP’s estimates, an FPGA made with 45-nm transistors and a grid of nanowires 4.5 nanometres across would only be 4 per cent as large as a regular FPGA manufactured using the 45-nm process.